library ieee;
use ieee.std_logic_1164.all;

entity reg is
	generic (
		size  	: in  positive
	);
	port (
		clk		: in  std_logic;
		reset		: in	std_logic;

		store		: in  std_logic;

		data_in	: in  std_logic_vector(size-1 downto 0);
		data_out : out std_logic_vector(size-1 downto 0)
	);
end entity;

architecture behaviour of reg is
	signal reg_i, reg_o : std_logic_vector(size-1 downto 0);
begin
	reg_i <= data_in when store = '1' else reg_o;
	data_out <= reg_o;

	process(clk, reset) begin
		if (clk'event and clk = '1') then
			if (reset = '1') then
				reg_o <= (others => '0');
			else
				reg_o <= reg_i;
			end if;
		end if;
	end process;
end architecture;

